With the continuous scaling down of the semiconductor process technology node, the traditional planar-MOSFET is facing increasing challenges, such as the remarkable leakage current, the serious short channel effect, and the degraded subthreshold performance. With the scaling of the critical dimension of MOS device, the device fabrication relies increasingly on high precision lithography processes, which greatly limits the performance improvement of the planar-MOSFET. Thus, recently more and more researches explore MOSFETs with three-dimensional structures, and especially focus on the FinFETs and the multi-gate devices such as the representatively gate-all-around nanowire MOSFETs. The FinFET now has been considered as a novel device structure by the industry which will continue the scaling-down trend of the semiconductor process, and is expected to realize mass production in sub-20 nm technology node. The gate-all-around nanowire MOSFET is supposed to be the mainstream device structure for the next generation as a successor of the FinFET.
However, most of the gate-all-around MOSFETs studies presently are configured to have conductive channels parallel to the substrate surface. That is to say, suspended conductive channels are formed on the substrate surface before the gate-all-around gate electrode is fabricated. Such device structure makes a high demand for the fabrication process of the device, especially for the process of forming the suspended conductive channels, which cannot be realized easily by a mature manufacturing process presently. Another disadvantage of this structure is that the critical dimension of the gate electrode is still defined by the traditional lithography techniques, which limits the further reduction of the device size.
Thus, vertical channel gate-all-around MOSFET devices have been raised. FIG. 1 (Mark Bohr, IEDM, 2011) illustrates a conventional gate-all-around MOSFET structure including source/drain electrodes 103, conductive channels 102 and a gate electrode 101, wherein the conductive channels 102 are perpendicular to the substrate surface, and the gate electrode 101 surrounds the conductive channels 102 so as to form the gate-all-around device structure. A remarkable advantage of this structure is that it can be fabricated easily to achieve a desired subthreshold performance. Another noble advantage is that the critical dimension of the gate electrode can be defined by the thickness of the deposited layer through the deposition process without any photolithography technologies so that the device size can be further decreased easily. However, recently there still lacks a manufacturing process for the gate-all-around MOSFET with vertical channels which is compatible with the traditional CMOS process and allows the device to be fabricated by the conventional equipments so as to avoid the cost increasing and to overcome the process difficulties of the device with scaled size. Thus, it is significant to develop a method for fabricating vertical channel gate-all-around MOSFETs compatible with the traditional CMOS process.